Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations

Design Space Exploration of Network Processor Architectures

We describe an approach to explore the design space for architectures of packet processing devices on the system level. Our method is specific to the application domain of packet processors and is based on (1) models for packet processing tasks, a specification of the workload generated by traffic streams, and a description of the feasible space of architectures including computation and commun...

Compact massive MIMO antenna array for small 5G base stations

Design space exploration tools for the ByoRISC configurable processor family

In this paper, the ByoRISC (“Build your own RISC”) configurable application-specific instruction-set processor (ASIP) family is presented. ByoRISCs, as vendor-independent cores, provide extensive architectural parameters over a baseline processor, which can be customized by application-specific hardware extensions (ASHEs). Such extensions realize multi-input multi-output (MIMO) custom instructi...

Design Space Exploration for Massively Parallel Processor Arrays

In this paper, we describe an approach for the optimization of dedicated co-processors that are implemented either in hardware (ASIC) or configware (FPGA). Such massively parallel co-processors are typically part of a heterogeneous hardware/software-system. Each coprocessor is a massive parallel system consisting of an array of processing elements (PEs). In order to decide whether to map a comp...

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor

DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework Methodology for Rapid Accelerator Development Applied to Financial Applications A Reconfigurable Application Specific Instruction Set Processor. Adaptive processor architecture invited paperMichael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Cross-architectura...